Examples of Shifters Codes

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Electronics and Communication parts with function

This programs are examples of good and no error, and running program with a correct and have a reliable outputs.

—shifter-left—

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shiftleft_8 is

Port ( A,B : in  STD_LOGIC_VECTOR (7 downto 0);

outleft : out  STD_LOGIC_VECTOR (7 downto 0);

zeroact : out std_logic);

end shiftleft_8;

architecture structural of shiftleft_8 is

signal signa6,signa7,zact :  STD_LOGIC_VECTOR (7 downto 0);

component shifter_stage1 is

Port ( in25 : in  STD_LOGIC_VECTOR (7 downto 0);

stage1 : in          STD_LOGIC;

out10 : out  STD_LOGIC_VECTOR (7 downto 0));

end component;

component shifters_stage2 is

Port ( in27 : in  STD_LOGIC_VECTOR (7 downto 0);

stage2 : in          STD_LOGIC;

out12 : out  STD_LOGIC_VECTOR (7 downto 0));

end component;

component shifters_stage4 is

Port ( in29 : in  STD_LOGIC_VECTOR (7 downto 0);

stage4 : in           STD_LOGIC;

out14 : out  STD_LOGIC_VECTOR (7 downto 0));

end component;

begin

shiftleft0: shifter_stage1 port map (A,B(0),signa6);

shiftleft1: shifters_stage2 port map (signa6,B(1),signa7);

shiftleft2: shifters_stage4 port map (signa7,B(2),zact);

outleft <= zact;

zeroact <= ‘1’

when zact = “00000000”

else ‘0’;

end structural;

—shifter-right—

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shiftright_8 is

Port ( D,E : in  STD_LOGIC_VECTOR (7 downto 0);

outright : out  STD_LOGIC_VECTOR (7 downto 0);

zeroact : out std_logic);

end shiftright_8;

architecture structural of shiftright_8 is

signal signa15,signa16,zact : STD_LOGIC_VECTOR (7 downto 0);

component  shiftersright_stage1 is

Port ( in31 : in  STD_LOGIC_VECTOR (7 downto 0);

stage1right : in  STD_LOGIC;

out16 : out  STD_LOGIC_VECTOR (7 downto 0));

end component;

component  shiftersright_stage2 is

Port ( in33 : in  STD_LOGIC_VECTOR (7 downto 0);

stage2right : in  STD_LOGIC;

out18 : out  STD_LOGIC_VECTOR (7 downto 0));

end component;

component shiftersright_stage4 is

Port ( in35 : in  STD_LOGIC_VECTOR (7 downto 0);

stage4right : in  STD_LOGIC;

out20 : out  STD_LOGIC_VECTOR (7 downto 0));

end component;

begin

shiftright0: shiftersright_stage1 port map (D,E(0),signa15);

shiftright1: shiftersright_stage2 port map (signa15,E(1),signa16);

shiftright2: shiftersright_stage4 port map (signa16,E(2),zact);

outright <= zact;

zeroact <= ‘1’

when zact = “00000000”

else ‘0’;

end structural;

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